Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel

ABSTRACT

Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) and methods of fabricating silicon carbide MOSFETs are provided. The silicon carbide MOSFETs have an n-type silicon carbide drift layer, spaced apart p-type silicon carbide regions in the n-type silicon carbide drift layer and having n-type silicon carbide regions therein, and a nitrided oxide layer. The MOSFETs also have n-type shorting channels extending from respective ones of the n-type silicon carbide regions through the p-type silicon carbide regions to the n-type silicon carbide drift layer. In further embodiments, silicon carbide MOSFETs and methods of fabricating silicon carbide MOSFETs are provided that include a region that is configured to self-deplete the source region, between the n-type silicon carbide regions and the drift layer, adjacent the oxide layer, upon application of a zero gate bias.

RELATED APPLICATIONS

[0001] The present application claims priority from U.S. ProvisionalApplication Ser. No. 60/237,822, entitled “Method of Improving anInterface Between a Silicon Carbide Layer and an Oxide Layer,” U.S.Provisional Application Ser. No. 60/237,426 entitled “SiC Power MOSFETand Method of Fabrication” which were filed Oct. 3, 2000, U.S.Provisional Application Ser. No. 60/294,307 entitled “Method of N₂OGrowth of an oxide layer on a Silicon Carbide Layer” filed May 30, 2001,and U.S. patent application Ser. No. 09/834,283, entitled “Method of N₂OAnnealing an oxide layer on a Silicon Carbide Layer” filed Apr. 12,2001, the disclosures of which are incorporated by reference as if setforth fully herein.

FIELD OF THE INVENTION

[0002] The present invention relates to semiconductor devices and thefabrication of semiconductor devices and more particularly, to siliconcarbide (SiC) metal-oxide semiconductor transistors (MOSFETs) and thefabrication of such MOSFETs.

BACKGROUND OF THE INVENTION

[0003] To make a high current, high voltage, low on-resistance, verticalSiC power MOSFET has, so far, been impractical, at least in part, due tothe poor surface mobility of electrons in the inversion layer. Recently,some processing techniques have been developed on a lateral MOSFETstructure, which result in an improved surface electron mobility.However, a power MOSFET structure may involve additional processingincluding, for example, anneals at temperatures of greater than 1500° C.for the activation of p-type dopants, for example, p-well/p+contact/p-Junction Termination Extension (JTE) implants. Such annealsmay have detrimental impact on the performance of power MOSFETsfabricated using such techniques.

[0004] A number of silicon carbide power MOSFET structures have beendescribed in the literature. See e.g. U.S. Pat. No. 5,506,421; A. K.Agarwal, J. B. Casady, L. B. Rowland, W. F. Valek, M. H. White, and C.D. Brandt, “1.1 kV 4H—SiC Power UMOSFET's,” IEEE Electron DeviceLetters, Vol. 18, No. 12, pp. 586-588, December 1997; A. K. Agarwal, J.B. Casady, L. B. Rowland, W. F. Valek and C. D. Brandt, “1400 V 4H—SiCPower MOSFETs,” Materials Science Forum Vols. 264-268, pp. 989-992,1998; J. Tan, J. A. Cooper, Jr., and M. R. Melloch, “High-VoltageAccumulation-Layer UMOSFETs in 4H—SiC,” IEEE Electron Device Letters,Vol. 19, No. 12, pp. 487-489, December 1998; J. N. Shenoy, J. A. Cooperand M. R. Melloch, “High-Voltage Double-Implanted Power MOSFET's in6H—SiC,” IEEE Electron Device Letters, Vol. 18, No. 3, pp. 93-95, March1997; J. B. Casady, A. K. Agarwal, L. B. Rowland, W. F. Valek, and C. D.Brandt, “900 V DMOS and 1100 V UMOS 4H—SiC Power FETs,” IEEE DeviceResearch Conference, Ft. Collins, Colo., June 23-25, 1997; R. Schörner,P Friedrichs, D. Peters, H. Mitlehner, B. Weis and D. Stephani, “RuggedPower MOSFETs in 6H—SiC with Blocking Capability up to 1800 V,”Materials Science Forum Vols. 338-342, pp. 1295-1298, 2000; V. R.Vathulya and M. H. White, “Characterization of Channel Mobility onImplanted SiC to determine Polytype suitability for the Power DIMOSstructure,” Electronic Materials Conference, Santa Barbara, Calif., Jun.30-Jul. 2, 1999; A. V. Suvorov, L. A. Lipkin, G. M. Johnson, R. Singhand J. W. Palmour, “4H—SiC Self-Aligned Inplant-Diffused Structure forPower DMOSFETs,” Materials Science Forum Vols. 338-342, pp. 1275-1278,2000; P. M. Shenoy and B. J. Baliga, “The Planar 6H—SiC ACCUFET: A NewHigh-Voltage Power MOSFET Structure,” IEEE Electron Device Letters, Vol.18, No. 12, pp. 589-591, December 1997; Ranbir Singh, Sei-Hyung Ryu andJohn W. Palmour, “High Temperature, High Current, 4H—SiC Accu-DMOSFET,”Materials Science Forum Vols. 338-342, pp. 1271-1274, 2000; Y. Wang, C.Weitzel and M. Bhatnagar, “Accumulation-Mode SiC Power MOSFET DesignIssues,” Materials Science Forum Vols. 338-342, pp. 1287-1290, 2000; andA. K. Agarwal, N. S. Saks, S. S. Mani, V. S. Hegde and P. A. Sanger,“Investigation of Lateral RESURF, 6H—SiC MOSFETs,” Materials ScienceForum Vols. 338-342, pp. 1307-1310, 2000.

[0005] The existing SiC structures can be divided into three categories:(1) Trench or UMOSFET, (2) Vertical Doubly Implanted MOSFET (DIMOSFET),and (3) Lateral Diffused MOSFET (LDMOSFET). These structures are shownin FIGS. 1A, 1B, 1C and 1D. With the Trench MOSFET illustrated in FIG.1A, however, it may be difficult to achieve a high breakdown voltage anda reproducible high inversion layer mobility along the sidewalls of thetrench. Consequently, the on-resistance may become very high, which mayrender the structure impractical. The lateral DMOSFET, illustrated inFIGS. 1C and 1D, may suffer from high electric field in the gate oxideand higher on-resistance as compared to the vertical DIMOSFET for agiven breakdown voltage.

[0006] The vertical DIMOSFET structure, illustrated in FIG. 1B, is avariation of the Diffused (DMOSFET) structure employed in silicontechnology. Typically, the p-wells are implanted with Al or Boron, thesource regions (n⁺) are implanted with nitrogen or phosphorus, and thep⁺ regions are usually implanted with Al. The implants are activated attemperatures between 1400° C.-1700° C. The contacts to n⁺ layers aremade with nickel (Ni) and annealed and the contacts to p⁺ are made byNi, Ti or Ti/Al. Both contacts are annealed at high temperatures. Thegate dielectric is, typically, either thermally grown (Thermal SiO₂) ordeposited using Low Pressure Chemical Vapor Deposition (LPCVD) techniqueand subsequently annealed in various ambients. The deposited dielectricmay be SiO₂ or an Oxide/Nitride/Oxide (ONO) stack. One difficulty withthe DIMOSFET structure may be the poor mobility of inversion layerelectrons, which can result in a very high on-resistance. The cause ofsuch a problem has been attributed to a high density of interface statesnear the conduction band edge as shown in FIG. 2. See R. Schorner, P.Friedrichs, D. Peters, and D. Stephani, “Significantly ImprovedPerformance of MOSFETs on Silicon Carbide using the 15R—SiC Polytype,”IEEE Electron Device Letters, Vol. 20, No. 5, pp. 241-244, May 1999.

[0007] The interface states near the conduction band edge tend to trapthe otherwise free electrons from the inversion layer leaving arelatively small number of free electrons in the inversion layer. Alsothe trapped electrons may create negatively charged states at theinterface which coulomb scatter the free electrons. The reduced numberof free electrons and the increased scattering may reduce the conductionof current from source to drain, which may result in low effectivemobility of electrons and a high on-resistance. Several factors havebeen attributed to the high density of states near the conduction bandedge: (1) carbon or silicon dangling bonds, (2) carbon clusters, and (3)Si—Si bonds creating a thin amorphous silicon layer at the interface.See S. T. Pantelides, “Atomic Scale Engineering of SiC DielectricInterfaces,” DARPA/MTO High Power and ONR Power Switching MURI Reviews,Rosslyn, Va., Aug. 10-12, 1999 and V. V. Afanas'ev, M. Bassler, G.Pensl, and M. Schulz, “Intrinsic SiC/SiO₂ Interface States,” Phys. Stat.Sol. (a), Vol. 162, pp. 321-337, 1997.

[0008] In addition to the high density of interface states, severalother mechanisms have also been attributed to the poor mobility ofinversion layer electrons: (1) Al segregating out of the Al-doped,p-type SiC, and (2) Surface roughness created by the high temperatureactivation of implanted impurities. See S. Sridevan, P. K. McLarty, andB. J. Baliga, “On the Presence of Aluminum in Thermally Grown Oxides on6HSilicon Carbide,” IEEE Electron Device Letters, Vol. 17, No. 3, pp.136-138, March 1996 and M. A. Capano, S. Ryu, J. A. Cooper, Jr., M. R.Melloch, K. Rottner, S. Karlsson, N. Nordell, A. Powell, and D. E.Walker, Jr., “Surface Roughening in Ion Implanted 4H-Silicon Carbide,”Journal of Electronic Materials, Vol. 28, No. 3, pp. 214-218, March,1999. Researchers from Purdue University have concluded that a directcorrelation exists between the inversion layer electron mobility and theimplant activation temperature. Such research has concluded that lowerimplant activation temperature (1200° C.) leads to higher electronmobility and higher activation temperature (1400° C.) results in poorelectron mobility. See M. K. Das, J. A. Cooper, Jr., M. R. Melloch, andM. A. Capano, “Inversion Channel Mobility in 4H— and 6H—SiC MOSFETs,”IEEE Semiconductor Interface Specialists Conference, San Diego, Calif.,Dec. 3-5, 1998. These results have been obtained on planar MOSFETs (FIG.3), which do not utilize an implantation of the p-well. The p-wellimplanted impurity (Al or Boron) typically requires at least a 1500° C.activation temperature.

[0009] The so-called “ACCUFET” structure is shown in FIG. 4. It resultsin high electron mobility due to conduction across an accumulation layerinstead of an inversion layer. In this structure, the p-well isimplanted using Al in such a manner so as to leave a thin unimplantedn-type surface layer. This n-type layer is fully depleted due to thebuilt-in voltage of the pn junction. However, the implant activationtemperature is typically limited to 1400° C. to avoid surface roughnessas indicated before. The doping of the remaining n-layer is the same asthe doping of the grown n-type layer. This structure has shown highelectron mobility in 6H—SiC but very poor electron mobility in 4H—SiC.

[0010] Sridevan and Alok have reported high electron mobility in 4H—SiCin a planar MOSFET on a p-type epitaxial layer (p-epi). S. Sridevan andB. Jayant Baliga, “Lateral N-Channel Inversion Mode 4H—SiC MOSFET's,”IEEE Electron Device Letters, Vol. 19, No. 7, pp. 228-230, July 1998; D.Alok, E. Arnold, and R. Egloff, “Process Dependence of Inversion LayerMobility in 4H—SiC Devices,” Materials Science Forum Vols. 338-342, pp.1077-1080, 2000. However, this is not a high voltage power MOSFETstructure. By using p-epi, the problems associated with p-wellactivation and resulting surface roughness may potentially be avoided. Adeposited oxide was used and the activation temperature of nitrogenimplants for the source and drain regions kept to a minimum (1250° C.)to avoid surface roughness. The contacts to the source and drain regionswere not annealed in order to protect the gate oxide/SiC interface. Thehigh electron mobility has been attributed to the special wet anneal ofthe deposited SiO₂ layer. This anneal was done at 1100° C. in N₂ bubbledthrough de-ionized (DI) water at 98° C. for 400 min, followed by an insitu Ar anneal at 1100° C. for 60 min, followed by a 950° C. wet N₂anneal for 60 min. The anneal was performed to densify the depositedoxide and reduce the interface state density.

[0011] Unfortunately, this approach suffers from reproducibility.Several groups, including researches at Rensealar Polytechnic Institute(RPI), Purdue University, and Cree, Inc. have been unsuccessful in theirattempts to duplicate this result.

[0012] Another method that has been reported as showing promise is thecounter-doping method. K. Ueno and Tadaaki Oikawa, “Counter-DopedMOSFET's of 4—HSiC,” IEEE Electron Device Letters, Vol. 20, No. 12, pp.624-626, December 1999. Again, this technique has been implemented onplanar MOSFETs without the p-well implant. This is not a high voltagepower MOSFET structure. By using p-epi, the problems associated withp-well activation and resulting surface roughness may be avoided. In thecounter-doping method, a thin layer of n-type impurity such as Nitrogenis implanted between the source and drain. The implant is activated at alow temperature (1300° C.) to avoid surface roughness. The dopingdensity of the n-type region can be controlled by controlling the doseand energy of the n-type implant. By relaxing the surface field withthis implant, higher channel mobilities have been reported.

[0013] Recently, annealing of a thermal oxide in a nitric oxide (NO)ambient has shown promise in a planar 4H—SiC MOSFET structure notrequiring a p-well implant. See M. K. Das, L. A. Lipkin, J. W. Palmour,G. Y. Chung, J. R. Williams, K. McDonald, and L. C. Feldman, “HighMobility 4H—SiC Inversion Mode MOSFETs Using Thermally Grown, NOAnnealed SiO₂,” IEEE Device Research Conference, Denver, Colo., Jun.19-21, 2000 and G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, R.A. Weller, S. T. Pantelides, L. C. Feldman, M. K. Das, and J. W.Palmour, “Improved Inversion Channel Mobility for 4H—SiC MOSFETsFollowing High Temperature Anneals in Nitric Oxide,” IEEE ElectronDevice Letters accepted for publication, the disclosures of which areincorporated by reference as if set forth fully herein. This anneal isshown to significantly reduce the interface state density near theconduction band edge. G. Y. Chung, C. C. Tin, J. R. Williams, K.McDonald, M. Di Ventra, S. T. Pantelides, L. C. Feldman, and R. A.Weller, “Effect of nitric oxide annealing on the interface trapdensities near the band edges in the 4H polytype of silicon carbide,”Applied Physics Letters, Vol. 76, No. 13, pp. 1713-1715, March 2000, thedisclosure of which is incorporated herein as if set forth fully. Highelectron mobility (35-95 cm²/Vs) is obtained in the surface inversionlayer due to the improved MOS interface.

[0014] Unfortunately, NO is a health hazard having a National FireProtection Association (NFPA) health danger rating of 3, and theequipment in which postoxidation anneals are typically performed is opento the atmosphere of the cleanroom. They are often exhausted, but thedanger of exceeding a safe level of NO contamination in the room is notnegligible.

[0015] Growing the oxide in N₂O is possible. J. P. Xu, P. T. Lai, C. L.Chan, B. Li, and Y. C. Cheng, “Improved Performance and Reliability ofN₂O-Grown Oxynitride on 6H—SiC,” IEEE Electron Device Letters, Vol. 21,No. 6, pp. 298-300, June 2000, the disclosure of which is incorporatedby reference as if set forth fully herein. Postgrowth nitridation of theoxide on 6H—SiC in N₂O at a temperature of 1100° C. has also beeninvestigated by Lai et al. P. T. Lai, Supratic Chakraborty, C. L. Chan,and Y. C. Cheng, “Effects of nitridation and annealing on interfaceproperties of thermally oxidized SiO₂/SiC metal-oxide-semiconductorsystem,” Applied Physics Letters, Vol. 76, No. 25, pp. 3744-3746, June2000, the disclosure of which is incorporated by reference as if setforth fully herein. However, Lai et al. concluded that such treatmentdeteriorates the interface quality which may be improved with asubsequent wet or dry anneal in O₂ which may repair the damage inducedby nitridation in N₂O. Moreover, even with a subsequent O₂ anneal, Laiet al. did not see any significant reduction in interface state densityas compared to the case without nitridation in N₂O. However, this workutilized 6H—SiC and it is not clear whether it would work on 4H—SiC,since many improvements to 6H—SiC MOSFETs have not previously resultedin any significant improvement in 4H—SiC MOSFETs.

SUMMARY OF THE INVENTION

[0016] Embodiments of the present invention provide silicon carbidemetal-oxide semiconductor field effect transistors (MOSFETs) and methodsof fabricating silicon carbide MOSFETs having an n-type silicon carbidedrift layer, spaced apart p-type silicon carbide regions within thedrift layer and having n-type silicon carbide regions therein, and anoxide layer on the drift layer. The MOSFETs also have n-type shortingchannels extending from respective ones of the n-type silicon carbideregions to the n-type silicon carbide drift layer.

[0017] In particular embodiments of the present invention, the p-typesilicon carbide regions are spaced apart regions of silicon carbidehaving aluminum implanted therein. In further embodiments of the presentinvention, the n-type shorting channels are self-aligned with respectiveones of the p-type silicon carbide source regions.

[0018] In alternative embodiments of the present invention, an epitaxiallayer of silicon carbide is provided on the n-type silicon carbide driftlayer between the n-type shorting channels. In certain embodiments, theepitaxial layer of silicon carbide is on the n-type silicon carbidedrift layer and the p-type silicon carbide source regions. In suchembodiments of the present invention, the n-type shorting channels mayextend into and/or through the epitaxial layer of silicon carbide.

[0019] In further embodiments of the present invention, a gate contactis provided on the oxide layer. In particular embodiments of the presentinvention, the gate contact is p-type polysilicon.

[0020] In still firther embodiments of the present invention, the n-typeshorting channels are doped so that the n-type channels are selfdepleted regions when a zero volt gate bias is applied. In particularembodiments of the present invention, the shorting channels have a sheetcharge of less than about 10¹³ cm⁻². For example, the n-type shortingchannels may have a sheet charge corresponding to the sheet charge of anepitaxial layer of silicon carbide having a thickness of about 3500 Åand a carrier concentration of about 2×10¹⁶ cm⁻³. Furthermore, forembodiments of the present invention in 4H polytype silicon carbide, theinterface between the oxide layer and the n-type drift layer preferablyhas an interface state density of less than 10¹² eV⁻¹cm⁻² for energylevels between about 0.3 and about 0.4 eV of a conduction band energy of4H polytype silicon carbide.

[0021] In additional embodiments of the present invention, a siliconcarbide device is provided having a drift layer of n-type siliconcarbide and first regions of p-type silicon carbide in the drift layer.The first regions of p-type silicon carbide are spaced apart and haveperipheral edges which define a region of the drift layer therebetween.First regions of n-type silicon carbide having a carrier concentrationgreater than a carrier concentration of the drift layer are provided inthe first regions of p-type silicon carbide and are spaced apart fromthe peripheral edges of the first regions of p-type silicon carbide.Second regions of n-type silicon carbide having a carrier concentrationless than the carrier concentration of the first regions of n-typesilicon carbide extend from the first regions of n-type silicon carbideto the peripheral edges of the first regions of p-type silicon carbide.An oxide layer is provided on the drift layer, the first regions ofn-type silicon carbide and the second regions of n-type silicon carbide.

[0022] In particular embodiments of the present invention, the secondregions of n-type silicon carbide have a sheet charge of less than about10¹³ cm⁻². For example, the second regions of silicon carbide may have asheet charge corresponding to the sheet charge of an epitaxial layer ofsilicon carbide having a thickness of about 3500 Å and a carrierconcentration of about 2×10¹⁶ cm⁻³. Furthermore, the second regions ofn-type silicon carbide may have a depth of from about 0.05 μm to about 1μm. The second regions of n-type silicon carbide may also extend adistance of from about 0.5 μm to about 5 μm from the first regions ofn-type silicon carbide to the peripheries of the first regions of p-typesilicon carbide.

[0023] In further embodiments of the present invention utilizing 4Hpolytype silicon carbide, the interface state density of an interfacebetween the oxide layer and the drift layer, the first regions of n-typesilicon carbide and the second regions of n-type silicon carbide is lessthan about 10¹² eV⁻¹cm⁻² between about 0.3 and about 0.4 eV of theconduction band energy of 4H polytype silicon carbide.

[0024] In additional embodiments of the present invention, secondregions of p-type silicon carbide disposed in respective ones of thefirst regions of p-type silicon carbide are provided. The second regionsof p-type silicon carbide have a carrier concentration greater than thecarrier concentration of the first regions of silicon carbide. Thesecond regions of silicon carbide are also adjacent the first regions ofn-type silicon carbide and opposite the second regions of n-type siliconcarbide.

[0025] In particular embodiments of the present invention, the firstregions of p-type silicon carbide are spaced apart by a distance of fromabout 1 μm to about 10 μm. The first regions of p-type silicon carbidemay also have a carrier concentration of from about 1×10¹⁶ to about2×10¹⁹ cm⁻³.

[0026] Furthermore, source contacts on the first region of p-typesilicon carbide and the first region of n-type silicon carbide may alsobe provided. A layer of n-type silicon carbide having a carrierconcentration greater than the carrier concentration of the drift layerand disposed adjacent the drift layer opposite the oxide layer may alsobe provided. In such embodiments, a drain contact may be provided on thelayer of n-type silicon carbide.

[0027] In still further embodiments of the present invention, anepitaxial layer of silicon carbide is provided on the first p-typeregions and the drift layer of n-type silicon carbide. The secondregions of n-type silicon carbide extend into the epitaxial layer, thefirst regions of n-type silicon carbide extend through the epitaxiallayer and the oxide layer is on the epitaxial layer, the first regionsof n-type silicon carbide and the second regions of n-type siliconcarbide. The epitaxial layer may be undoped silicon carbide. Theepitaxial layer may also be n-type silicon carbide having sheet chargeof less than about 10¹³ cm². The epitaxial layer of silicon carbide mayalso be an epitaxial layer of silicon carbide having a thickness of fromabout 0.05 μm to about 1 μm. Preferably, the epitaxial layer of siliconcarbide has a thickness of from about 1000 to about 5000 A.

[0028] In additional embodiments of the present invention, secondregions of p-type silicon carbide disposed in respective ones of thefirst regions of p-type silicon carbide are provided. The second regionsof p-type silicon carbide have a carrier concentration greater than thecarrier concentration of the first regions of silicon carbide and areadjacent the first regions of n-type silicon carbide and opposite thesecond regions of n-type silicon carbide. Windows in the epitaxial layermay be positioned to expose the second regions of p-type silicon carbideand first source contacts provided within the window on the secondregions of p-type silicon carbide. Second source contacts may also beprovided on the first source contacts and the first regions of n-typesilicon carbide.

[0029] In various embodiments of the present invention, methods offabricating a silicon carbide device include implanting p-typeimpurities in a layer of n-type silicon carbide so as to provide firstregions of p-type silicon carbide, the first regions of p-type siliconcarbide being spaced apart and having peripheral edges which define aregion of the layer of n-type silicon carbide therebetween. N-typeimpurities are also implanted into the first regions of p-type siliconcarbide to provide first regions of n-type silicon carbide having acarrier concentration greater than a carrier concentration of the layerof silicon carbide, the first regions of n-type silicon carbide beingspaced apart from the peripheral edges of the first regions of p-typesilicon carbide. N-type impurities are implanted into the first regionsof p-type silicon carbide to provide second regions of n-type siliconcarbide having a carrier concentration less than the carrierconcentration of the first regions of n-type silicon carbide and whichextend from the first regions of n-type silicon carbide to theperipheral edges of the first regions of p-type silicon carbide. Anoxide layer is patterned on the drift layer, the first regions of n-typesilicon carbide and the second regions of n-type silicon carbide so asto provide a gate oxide.

[0030] In particular embodiments, implanting p-type impurities,implanting n-type impurities to provide first regions of n-type siliconcarbide and implanting n-type impurities to provide second regions ofn-type silicon carbide are provided by patterning a first mask on thelayer of n-type silicon carbide, the first mask having openingscorresponding to the first regions of p-type silicon carbide so as toexpose portions of the layer of n-type silicon carbide and thenimplanting p-type impurities into the layer of n-type silicon carbideutilizing the first mask and implanting n-type impurities into the firstregions of p-type silicon carbide utilizing the first mask. A secondmask is patterned on the layer of n-type silicon carbide, the secondmask having openings corresponding to the first regions of n-typesilicon carbide so as to expose portions of the layer of n-type siliconcarbide having the p-type and n-type impurities implanted therein.N-type impurities are implanted into the layer of n-type silicon carbideutilizing the second mask.

[0031] In certain embodiments of the present invention, implantingn-type impurities into the layer of n-type silicon carbide utilizing thefirst mask is followed by activating the implanted impurities byannealing at a temperature of at least about 1500° C. Preferably, thep-type impurities are aluminum.

[0032] Furthermore, the second mask may be patterned so that the secondregions of n-type silicon carbide extend a distance of from about 0.5 μmto about 5 μm from the first regions of n-type silicon carbide to theperipheries of the first regions of p-type silicon carbide. Also,impurities may be implanted so that the second regions of n-type siliconcarbide have a sheet charge of less than about 10¹³ cm⁻². The n-typeimpurities may be implanted utilizing an implant energy so as to providesecond regions of n-type silicon carbide have a depth of from about 0.05μm to about 1 μm.

[0033] In particular embodiments of the present invention, the oxidelayer is thermally grown. The oxide layer may also be provided byforming an oxide-nitrideoxide (ONO) layer. Preferably, the first oxidelayer of the ONO structure is thermally grown. In any event, the oxidelayer may be annealed in an NO environment or an N₂O environment. It isalso preferred that the annealing provides an interface state density ofan interface between the oxide layer and the drift layer, the firstregions of n-type silicon carbide and the second regions of n-typesilicon carbide of less than about 10¹² eV⁻¹cm⁻² between about 0.3 andabout 0.4 eV of the conduction band energy of 4H polytype siliconcarbide. Such an interface state density may be determined as describedin Sze, Physics of Semiconductor Devices, 2nd Edition, John Wiley &Sons, 1981, pp. 383-390.

[0034] In still further embodiments of the present invention, p-typeimpurities are implanted into the layer of n-type silicon carbide so asto provide second regions of p-type silicon carbide disposed inrespective ones of the first regions of p-type silicon carbide. Thesecond regions of p-type silicon carbide have a carrier concentrationgreater than the carrier concentration of the first regions of siliconcarbide. The second regions of silicon carbide are also adjacent thefirst regions of n-type silicon carbide and opposite the second regionsof n-type silicon carbide.

[0035] In certain embodiments of the present invention, the first maskhas openings which are spaced apart by a distance of from about 1 μm toabout 10 μm. Also, n-type impurities may be implanted into a face of thelayer of n-type silicon carbide opposite the oxide layer so as toprovide a second layer of n-type silicon carbide having a carrierconcentration greater than the carrier concentration of the layer ofn-type silicon carbide. A drain contact may then be formed on the secondlayer of n-type silicon carbide. Furthermore, the layer of n-typesilicon carbide may be a silicon carbide substrate.

[0036] In still further embodiments of the present invention, implantingp-type impurities, implanting n-type impurities to provide first regionsof n-type silicon carbide and implanting n-type impurities to providesecond regions of n-type silicon carbide may be provided by patterning afirst mask on the layer of n-type silicon carbide, the first mask havingopenings corresponding to the first regions of p-type silicon carbide soas to expose portions of the layer of n-type silicon carbide. Thenp-type impurities (preferably, aluminum) are implanted into the layer ofn-type silicon carbide utilizing the first mask and the layer of n-typesilicon carbide and the first regions of p-type silicon carbide annealedat a temperature of at least about 1500° C. An epitaxial layer ofsilicon carbide is then grown on the layer of n-type silicon carbide andthe first regions of p-type silicon carbide. A second mask is patternedon the layer of n-type silicon carbide. The second mask has openingscorresponding to the second regions of n-type silicon carbide so as toexpose portions of the first regions of p-type silicon carbide. N-typeimpurities are implanted into the epitaxial layer n-type silicon carbideutilizing the second mask. A third mask is patterned on the layer ofn-type silicon carbide. The third mask has openings corresponding to thefirst regions of n-type silicon carbide and exposes portions of thefirst regions of p-type silicon carbide. N-type impurities are implantedinto the first regions of p-type silicon carbide and the epitaxial layerof silicon carbide utilizing the third mask. The oxide layer ispatterned on the epitaxial layer, the first regions of n-type siliconcarbide and the second regions of n-type silicon carbide to provide agate oxide.

[0037] In still further embodiments of the present invention, the stepof growing an epitaxial layer of silicon carbide is provided by growingan undoped epitaxial layer of silicon carbide. In still furtherembodiments of the present invention, the step of growing an epitaxiallayer of silicon carbide is provided by growing an epitaxial layer ofsilicon carbide having a sheet charge of less than about 10¹³ cm⁻².Furthermore, the epitaxial layer of silicon carbide may be grown to athickness of from about 0.05 μm to about 1 μm. Preferably, the epitaxiallayer of silicon carbide is grown to thickness of from about 1000 toabout 5000 Å.

[0038] In additional embodiments of the present invention, the step ofannealing is preceded patterning a fourth mask, the fourth mask being onthe layer of n-type silicon carbide and the first regions of p-typesilicon carbide and having opening therein corresponding to secondregions of p-type silicon carbide disposed in respective ones of thefirst regions of p-type silicon carbide the second regions of siliconcarbide being adjacent the first regions of n-type silicon carbide andopposite the second regions of n-type silicon carbide. P-type impuritiesare implanted utilizing the fourth mask so that the second regions ofp-type silicon carbide have a carrier concentration greater than thecarrier concentration of the first regions of silicon carbide.Furthermore, windows may be formed in the epitaxial layer positioned toexpose the second regions of p-type silicon carbide First sourcecontacts may also be formed within the window on the second regions ofp-type silicon carbide. Second source contacts may be formed on thefirst source contacts and the first regions of n-type silicon carbide.

BRIEF DESCRIPTION OF THE DRAWINGS

[0039]FIG. 1A is an illustration of a conventional UMOSFET;

[0040]FIG. 1B is an illustration of a conventional DIMOSFET;

[0041]FIGS. 1C and 1D are illustrations of conventional LDMOSTs;

[0042]FIG. 2 is a graph of interface trap density versus voltage for ONOand thermally grown oxides on 6H and 4H polytpe silicon carbide;

[0043]FIG. 3 is a schematic illustration of a conventional planarMOSFET;

[0044]FIG. 4 is a schematic illustration of an n-channel SiC ACCUFET;

[0045]FIG. 5 is a schematic illustration of a rough SiC/SiO₂ interfaceand a discontinuous inversion layer of electrons;

[0046]FIG. 6 is a schematic illustration of a SiC MOSFET according toembodiments of the present invention;

[0047]FIG. 7 is a schematic illustration of a SiC MOSFET according tofurther embodiments of the present invention;

[0048]FIGS. 8A through 8H illustrate processing steps in the fabricationof MOSFETS according to various embodiments of the present invention;

[0049]FIGS. 9A through 9J illustrate processing steps in the fabricationof MOSFETS according to further embodiments of the present invention;

[0050]FIGS. 10A through 10C illustrate operation of a shorting channelaccording to particular embodiments of the present invention;

[0051]FIG. 11 is a graph of an exemplary doping profile suitable for usein embodiments of the present invention;

[0052]FIG. 12 is a graph of interface trap density (Dit) versus energylevel from the conduction band (E_(C)-E) for NO and N₂O post oxidationannealing;

[0053]FIG. 13 is graph of the forward I-V characteristics for a deviceaccording to embodiments of the present invention; and

[0054]FIG. 14 is a graph of channel mobility versus gate voltage for adevice according to embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0055] The present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in whichpreferred embodiments of the invention are shown. This invention may,however, be embodied in many different forms and should not be construedas limited to the embodiments set forth herein; rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the invention to thoseskilled in the art. As illustrated in the Figures, the sizes of layersor regions are exaggerated for illustrative purposes and, thus, areprovided to illustrate the general structures of the present invention.Like numbers refer to like elements throughout. It will be understoodthat when an element such as a layer, region or substrate is referred toas being “on” another element, it can be directly on the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” another element, there areno intervening elements present.

[0056] Embodiments of the present invention provide silicon carbideMOSFETs and/or methods of fabricating silicon carbide MOSFETs which mayreduce the performance degradation of the device as a result of theinterface between SiC and the oxide of the MOSFET. As is clear from theprevious discussion, in conventional devices utilizing conventionalfabrication techniques, the interface between SiC and SiO₂ may be ofinsufficient quality to provide high surface mobility of electrons in4H—SiC. While the inventors do not wish to be bound by any theory ofoperation, it has been proposed that the reduced electron mobility maybe due to a high density of interface traps or due to a rough interfaceresulting in surface potential fluctuations or both. The rough interfaceis schematically shown in FIG. 5. A high degree of roughness may lead toa discontinuous inversion layer of electrons and hence poor effectivemobility. This is especially true when the implanted p-well has beenannealed at temperatures in excess of 1500° C.

[0057] MOSFETs according to embodiments of the present invention areillustrated in FIG. 6. As seen in FIG. 6, in particular embodiments ofthe present invention, a lightly doped n⁻ drift layer 12 of siliconcarbide is on a n⁺ layer 10 of silicon carbide. The n⁻ drift layer 12may be a substrate or an epitaxial layer of silicon carbide and ispreferably 4H polytype silicon carbide. Preferably, the n⁻ drift layer12 has a carrier concentration of from about 1014 to about 10¹⁷ cm⁻³.Furthermore, the n⁺ layer 10 may be an implanted layer or region or anepitaxial layer. The n⁺ layer preferably has a carrier concentration offrom about 10¹⁸ to about 10²¹ cm⁻³.

[0058] As is further seen in FIG. 6, spaced apart regions of p-typesilicon carbide provide p-wells 20 in the n⁻ drift layer 12. The p-wells20 are, preferably, implanted with Al and annealed at a temperature ofat least about 1500° C. The p-wells 20 may have carrier concentrationsof from about 1×10¹⁶ to about 2×10¹⁹ cm⁻³ and may extend into the n⁻drift layer 12 from about 0.1 μm to about 3 μm. While various p-typedopants may be utilized, Al is preferred over Boron as the dopant of thep-wells 20 because Boron tends to diffuse over several microns whenannealed at temperatures exceeding 1500° C. Therefore, it may bedifficult to control the precise gap between the p-wells 20 (the regionwhich may be referred to as the JFET region 21). If this gap is toohigh, the field in the gate oxide can become too high when the device isin the blocking state. However, if the gap is too narrow, the resistanceof the JFET region 21 may become very high. Accordingly, gaps of fromabout 1 μm to about 10 μm are preferred. The particular gap utilized fora given device may depend upon the desired blocking voltage and on-stateresistance of the device.

[0059] Regions of n⁺ silicon carbide 24 and, optionally, regions of p⁺silicon carbide 22 are disposed within the p-wells 20. The regions of n⁺silicon carbide 24 are preferably spaced from about 0.5 μm to about 5 μmfrom the edge of the p-wells 20 adjacent the JFET region 21. Theoptional regions of p⁺ silicon carbide 22 are preferably adjacent theregions of n⁺ silicon carbide 24 and opposite the edge of the p-wells20. A thin layer of n-type silicon carbide, such as a layer doped withan n-type impurity such as nitrogen or phosphorus with a preselecteddose, extends from the regions of n⁺ silicon carbide 24 to the JFETregion of the n⁻ drift layer 12 adjacent the gate oxide 28 to provideshorting channels 26. The shorting channels 26 may be implanted withinthe p-well and activated at a temperature of at least about 1500° C.along with the p-well activation. Preferably, the shorting channels 26extend into the p-wells 20 to a depth of from about 0.05 μm to about 1μm. The doping of the shorting channels 26 may depend on the depth ofthe layer, the work function of the material for the gate contact 32 andthe doping of the p-wells 20 as described below with reference to FIGS.10A through 10C. However, in general, the shorting channels 26 may havea sheet charge of less than about 10¹³ cm⁻². It is also preferable toimplant the n-type impurity for the shorting channels 26 afterimplanting the Al for the p-wells 20 using the same mask to avoid havingto realign the mask such that the shorting channels 26 are self-alignedwith the p-wells 20. As described above, it is preferred that theshorting channels 26 not extend into the JFET region because extendingsuch layers into the JFET region may increase the electric field in theoxide when the device is in the blocking state.

[0060] The gate oxide 28 extends at least between the n⁺ regions ofsilicon carbide 24 and is preferably either a thermally grown oxide withan NO or N₂O anneal or Oxide/Nitride/Oxide (ONO) where the first oxideis a thermal oxide followed by an NO or N₂O anneal. The gate contactmaterial may be any suitable contact material, however, p-typepolysilicon may be preferred because of its high work function. Thethickness of the gate oxide 28 may depend on the work function of thematerial of the gate contact 32. However, in general, thicknesses offrom about 100 Å to about 5000 Å are preferred.

[0061] One or more source contacts 30 and a drain contact 34 are alsoprovided. Source contacts 30, are preferably formed of nickel (Ni) andmay be annealed at temperatures of from about 600° C. to about 1000° C.,for example, 825° C., so as to provide an ohmic contact to both the p⁺regions 22 and the n⁺ regions 24. The drain contact 34 may also be Ni orother such suitable material for forming an ohmic contact to n-typesilicon carbide.

[0062]FIG. 7 illustrates further alternative embodiments of the presentinvention which utilize a regrown epitaxial layer. As seen in FIG. 7, athin layer of silicon carbide 27 is re-grown on the p-wells 20 afterimplanting and annealing the p-wells and extends across the n-driftlayer 12 in the JFET region. The shorting channels 26′ may be formed ofthe regrown epitaxial layer or, preferably, they may be formed byimplantation in and/or through the regrown silicon carbide layer 27.Similarly, the n⁺ regions of silicon carbide 24 may also be formedthrough the regrown silicon carbide layer 27. The regrown siliconcarbide layer 27 may have a thickness of from about 0.05 μm to about 1μm, however, thicknesses of from about 1000 to about 5000 Å may bepreferred. Preferably, the regrown silicon carbide layer 27 is undoped,not intentionally doped or lightly doped. However, if the regrownsilicon carbide layer 27 forms the shorting channels 26′, the regrownsilicon carbide layer 27 should be n-type silicon carbide. Thus, theregrown silicon carbide layer 27 preferably has a sheet charge of lessthan about 10¹³ cm⁻² if the regrown silicon carbide layer 27 providesthe shorting channels. For example, a 3500 Å thick silicon carbide layer27 with a carrier concentration of 2×10¹⁶ may be particularly wellsuited to provide a device which is normally off at zero gate bias. Suchregrowth may reduce the surface roughness created by the implantactivation anneal. Moreover, regrowth puts the channel region on anepitaxial layer which may have reduced damage which may enable evenhigher channel mobility.

[0063] As is further seen in FIG. 7, because of the regrown siliconcarbide layer 27, a contact window is provided through the siliconcarbide layer 27 to provide a contact 30′ to the optional p⁺ regions 22or to the p-wells 20 if the p⁺ regions 22 are not present. The contact30′ may be made of any suitable material for forming an ohmic contact top-type silicon carbide, however, nickel is preferred.

[0064] While FIGS. 6 and 7 illustrate embodiments of the presentinvention as discrete devices, as will be appreciated by those of skillin the art, FIGS. 6 and 7 may be considered unit cells of devices havingmultiple cells. Thus, for example, additional unit cells may beincorporated into the devices illustrated in FIGS. 6 and 7 by dividingthe device along its central axis (illustrated as the vertical axis inFIGS. 6 and 7) and rotating the divided device about an axis of theperiphery of the devices illustrated in FIGS. 6 and 7 (the verticaledges of the devices illustrated in FIGS. 6 and 7). Accordingly,embodiments of the present invention include devices such as thoseillustrated in FIGS. 6 and 7 as well as devices having a plurality ofunit cells incorporating shorting channels illustrated in FIGS. 6 and 7.

[0065] Fabrication of devices according to embodiments of the presentinvention will now be described with reference to FIGS. 8A through 8Hand 9A through 9J. As seen in FIG. 8A, a mask 100 is formed andpatterned on the n-type layer 12 and impurities implanted into then-type layer 12 to provide the p-wells 20. Preferably, the impuritiesare Al implanted to the depths described above and to provide thedesired carrier concentrations when activated. After formation of thep-wells 20, an n-type implant 102 is performed utilizing the mask 100,see FIG. 8B. Suitable impurities for implantation of the n-type layerinclude nitrogen and phosphorous. Such impurities are implanted toprovide the shorting channel depth and carrier concentrations describedherein. An example of one suitable composite doping profile of thep-wells 20 and the n-type implant 102 is seen in FIG. 11. Afterimplantation of both the p-wells and the n-type layer 102, the resultingstructure is heated to a temperature of at least about 1500° C. andmaintained at that temperature for a time of from about 30 seconds toabout 60 minutes to activate the implanted impurities. Alternatively,such anneal may be carried out after implanting the n⁺ regions 24, thep⁺ regions 22 and the backside implant as seen in FIG. 8E.

[0066] As is seen in FIG. 8C, the mask 100 is removed and a mask 104 isformed and patterned and n-type impurities are implanted utilizing themask 104 to provide the n⁺ regions 24. The mask 104 is formed to providethe desired spacing between the periphery of the p-wells 20 and the n⁺regions 24 which defines the channel length of the shorting channels 26.Suitable n-type impurities include nitrogen and phosphorous.Furthermore, the impurities may be implanted to provide the dimensionsand carrier concentrations of the n⁺ regions 24 described herein.

[0067]FIG. 8D illustrates the formation of the optional p⁺ regions. Themask 104 is also removed and a mask 106 formed and patterned and p-typeimpurities implanted utilizing the mask 106 to provide the p⁺ regions22. The p-type impurities may be implanted to provide the dimensions andcarrier concentrations of the p⁺ regions 22 described herein.Preferably, the p-type impurity is aluminum, however, other suitablep-type impurities may also be utilized.

[0068]FIG. 8E illustrates the removal of the mask 106 as well as thecreation of the n⁺ layer 10, which may be formed by a backside implantof n-type impurities in a substrate or may be an epitaxial layer and maybe formed prior to FIG. 8A. Optionally, the anneal of the structuredescribed above may be performed to activate the implanted p-type andn-type impurities. Alternatively, in embodiments where the gate oxide isannealed after formation to improve the SiC/SiO₂ interface, theactivation of such impurities may be provided by such anneal.

[0069]FIG. 8F illustrates the formation and patterning of the gate oxide28. The gate oxide is preferably thermally grown and is a nitridedoxide. The nitrided oxide may be any suitable gate oxide, however, SiO₂,oxynitride or ONO may be preferred. Formation of the gate oxide or theinitial oxide of an ONO gate dielectric is preferably followed by ananneal in N₂O or NO so as to reduce defect density at the SiC/oxideinterface. In particular embodiments, the gate oxide is formed either bythermal growth or deposition and then annealed in an N₂O environment ata temperature of greater than about 1100° C. and flow rates of fromabout 2 to about 8 SLM which may provide initial residence times of theN₂O of from about 11 to about 45 seconds. Such formation and annealingof an oxide layer on silicon carbide are described in commonly assignedU.S. patent application Ser. No. 09/834,283, entitled “Method of N₂OAnnealing an Oxide Layer on a Silicon Carbide Layer” (Attorney DocketNo. 5308-156) or as described in U.S. Provisional Application Ser. No.______ entitled “Method of N₂O Growth of an oxide layer on a SiliconCarbide Layer” filed May 30, 2001, the disclosures of which areincorporated herein by reference as if set forth fully herein.Additionally, an N₂O grown oxide may also be utilized as described in J.P. Xu, P. T. Lai, C. L. Chan, B. Li, and Y. C. Cheng, “ImprovedPerformance and Reliability of N₂O-Grown Oxynitride on 6H—SiC,” IEEEElectron Device Letters, Vol. 21, No. 6, pp. 298-300, June 2000.Techniques as described in L. A. Lipkin and J. W. Palmour, “Lowinterface state density oxides on p-type SiC,” Materials Science ForumVols. 264-268, pp. 853-856, 1998 may also be utilized. Alternatively,for thermally grown oxides, a subsequent NO anneal of the thermallygrown SiO₂ layer may be provided to reduce the interface trap density asis described in M. K. Das, L. A. Lipkin, J. W. Palmour, G. Y. Chung, J.R. Williams, K. McDonald, and L. C. Feldman, “High Mobility 4H—SiCInversion Mode MOSFETs Using Thermally Grown, NO Annealed SiO₂,” IEEEDevice Research Conference, Denver, Colo., Jun. 19-21, 2000; G. Y.Chung, C. C. Tin, J. R. Williams, K. McDonald, R. A. Weller, S. T.Pantelides, L. C. Feldman, M. K. Das, and J. W. Palmour, “ImprovedInversion Channel Mobility for 4H—SiC MOSFETs Following High TemperatureAnneals in Nitric Oxide,” IEEE Electron Device Letters accepted forpublication; and G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, M.Di Ventra, S. T. Pantelides, L. C. Feldman, and R. A. Weller, “Effect ofnitric oxide annealing on the interface trap densities near the bandedges in the 4H polytype of silicon carbide,” Applied Physics Letters,Vol. 76, No. 13, pp. 1713-1715, March 2000. Oxynitrides may be providedas described in U.S. patent application Ser. No. ______, entitled “HighVoltage, High Temperature Capacitor Structures and Methods ofFabrication” filed Jun. 11, 2001, the disclosure of which isincorporated herein by reference as if set forth fully herein.

[0070] As an example of formation of a nitrided oxide layer, a layer ofoxide may be provided on a silicon carbide layer by oxidizing thesilicon carbide layer in an N₂O environment at a temperature of at leastabout 1200° C. A predetermined temperature profile and a predeterminedflow rate profile of N₂O are provided during the oxidation. Thepredetermined temperature profile and/or predetermined flow rate profilemay be constant or variable and may include ramps to steady stateconditions. The predetermined temperature profile and the predeterminedflow rate profile may be selected so as to reduce interface states ofthe oxide/silicon carbide interface with energies near the conductionband of SiC. The predetermined temperature profile may result in anoxidation temperature of greater than about 1200° C. Preferably, theoxidation temperature is about 1300° C. The duration of the oxidationmay vary depending on the thickness of the oxide layer desired. Thus,oxidation may be carried out for from about 15 minutes to about 3 hoursor longer.

[0071] Additionally, the predetermined flow rate profile may include oneor more flow rates of from about 2 Standard Liters per Minute (SLM) toabout 6 SLM. Preferably, the flow rates are from about 3.5 to about 4Standard Liters per Minute. Furthermore, formation of the resultingoxide layer may be followed by annealing the oxide layer in Ar or N₂.Such an annealing operation in Ar or N₂ may be carried out, for example,for about one hour.

[0072] The predetermined flow rate profile preferably provides avelocity or velocities of the N₂O of from about 0.37 cm/s to about 1.11cm/s. In particular, the predetermined flow rate profile preferablyprovides a velocity or velocities of the N₂O of from about 0.65 cm/s toabout 0.74 cm/s. Additionally, a wet reoxidation of the oxide layer mayalso be performed and/or the N₂O oxidation may be carried out in anenvironment with a fraction or partial pressure of steam.

[0073] Additionally, a layer of oxide may be formed on a silicon carbidelayer by forming the oxide layer on the silicon carbide layer in an N₂Oenvironment at a predetermined temperature profile which includes anoxidation temperature of greater than about 1200° C. and at apredetermined flow rate profile for the N₂O. The predetermined flow rateprofile may be selected to provide an initial residence time of the N₂Oof at least 11 seconds. Preferably, the initial residence time is fromabout 11 seconds to about 33 seconds. More preferably, the initialresidence time is from about 19 seconds to about 22 seconds.Additionally, a total residence time of the N₂O may be from about 28seconds to about 84 seconds. Preferably, the total residence time isfrom about 48 seconds to about 56 seconds.

[0074] A graph of interface state density versus energy level from theconduction band is illustrated in FIG. 12. Line 200 represents anunannealed oxide. Line 202 represents an oxide after a dry anneal in anNO environment. Line 204 represents an oxide after a dry anneal in anN₂O environment and line 206 represents an oxide after a wet anneal inan NO environment.

[0075]FIG. 8G illustrates formation of the gate contact 32. As describedabove, the gate contact 32 may be p-type polysilicon or may be othersuitable contact material and may be formed and patterned utilizingtechniques known to those of skill in the art. Alternatively, the oxide28 of FIG. 8F and the gate contact 32 may be formed and patternedtogether. Finally, FIG. 8H illustrates formation of the source and draincontacts 30 and 34 which may be formed by evaporative deposition,sputtering or other such techniques known to those of skill in the art.Preferably, the source and drain contacts 30 and 34 are nickel which isannealed at about 825° C. after formation so as to improve the qualityof the ohmic contact.

[0076]FIGS. 9A through 9J illustrate operations in the fabrication ofdevices according to alternative embodiments of the present inventionutilizing a regrown epitaxial layer. As seen in FIG. 9A, a mask 120 isformed and patterned on the n-type layer 12 and impurities implantedinto the n-type layer 12 to provide the p-wells 20. Preferably, theimpurities are Al implanted to the depths described above and to providethe desired carrier concentrations when activated. After formation ofthe p-wells 20, the mask 120 is removed and the mask 122 formed andpatterned to correspond to the optional p⁺ regions 22. A p-type implantis performed utilizing the mask 122, see FIG. 9B. Preferably, the p-typeimplant implants Al as the p-type impurity. Such impurities areimplanted to provide the dimensions and carrier concentrations for thep⁺ regions 22 described herein. After implantation of both the p-wells20 and the p⁺ regions 22, the resulting structure is heated to atemperature of at least about 1500° C. and maintained at thattemperature for a time of from about 30 seconds to about 60 minutes toactivate the implanted impurities.

[0077] As is seen in FIG. 9C, the mask 122 is removed and an epitaxiallayer 124 of SiC is formed on the p⁺ regions 22, the p-wells 20 and then-type silicon carbide layer 12 utilizing conventional techniques forgrowing silicon carbide epitaxial layers. As described above, theregrown epitaxial layer 124 is preferably undoped silicon carbide butmay also be lightly doped silicon carbide.

[0078]FIG. 9D illustrates the optional implantation of n-type impuritiesto provide the shorting channels 26′. As seen in FIG. 9D, a mask 126 isformed and patterned and n-type impurities implanted utilizing the mask126 to provide the shorting channels 26′. The mask 126 is formed toprovide the desired location of the shorting channels, preferably, sothat the shorting channels do not extend substantially into the JFETregion of the device. Suitable n-type impurities include nitrogen andphosphorous. Preferably, the impurities are implanted to provide thedimensions and carrier concentrations of the shorting channels 26′described herein.

[0079]FIG. 9E illustrates formation of the n⁺ regions 24. As seen inFIG. 9E, the mask 126 has been removed and a mask 128 formed andpatterned to provide openings corresponding to the n⁺ regions 24. Themask 128 is used to implant n-type impurities so as to provide thedimensions and carrier concentrations described herein for the n⁺regions 24.

[0080]FIG. 9F illustrates the removal of the mask 128 as well as thecreation of the n⁺ layer 10, which may be formed by a backside implantof n-type impurities in a substrate or may be an epitaxial layer and maybe formed prior to FIG. 9A. Optionally, an anneal of the structure,preferably at temperatures of less than 1500° C., may be performed toactivate the implanted p-type and n-type impurities. Alternatively, inembodiments where the gate oxide is annealed after formation to improvethe SiC/SiO₂ interface, the activation of such impurities may beprovided by such anneal.

[0081]FIG. 9G illustrates the formation and patterning of the gate oxide28. The gate oxide 28 is preferably thermally grown and is preferably anitrided oxide. The nitrided oxide may be any suitable gate oxide,however, SiO₂, oxynitride or ONO may be preferred. Formation of the gateoxide may be carried out as described above with reference to FIG. 8F.

[0082]FIG. 9H illustrates formation of source contacts 30′. As seen inFIG. 9H, windows are opened in the regrown layer 124 corresponding tothe location of the p⁺ regions 22. The contacts 30′ are then formed inthe window. FIG. 91 illustrates formation of the gate contact 32 and thesource contacts 30′. Alternatively, the oxide 28 of FIG. 9G and the gatecontact 32 may be formed and patterned together. As described above, thegate contact 32 may be p-type polysilicon or may be other suitablecontact material and may be formed and patterned utilizing techniquesknown to those of skill in the art. Source contacts 30′ may be formed byevaporative deposition, sputtering or other such techniques known tothose of skill in the art. Finally, FIG. 9J illustrates formation of thedrain contact 34 which may be formed by evaporative deposition,sputtering or other such techniques known to those of skill in the art.Preferably, the source and drain contacts 30′ and 34 are nickel which isannealed at temperature of from about 600° C. to about 1000° C., forexample, about 825° C., after formation so as to improve the quality ofthe ohmic contact.

[0083] As described above, embodiments of the present invention provideshorting channels 26 and 26′ between the JFET region of the device,through the p-wells 20 and to the n⁺ regions 24. In forming the shortingchannels 26 and 26′, the dose and energy of the n-type impurity ispreferably controlled so as to make the device normally off at zero gatebias. This can be done because there is self-depletion of the shallown-type layer from the built-in voltage of the pn junction, the workfunction difference of the gate metal and the SiC, and the net charge inthe oxide and the interface states. However, care should be taken sothat the n-layer is not completely depleted by the buried pn junction.This ensures the existence of a bulk channel under the thin accumulationlayer. The width of this bulk channel increases with positive gatebiases until an accumulation layer is formed at the MOS interface, asshown in FIGS. 10A through 10C. This accumulation layer may bediscontinuous due to surface roughness and fluctuations of the surfacepotential.

[0084]FIG. 10A illustrates the shorting channels 26 and 26′ when no gatebias is applied. As seen in FIG. 10B, the bulk channel, which is createdby positive gate bias, connects discontinuous surface accumulation layerregions, resulting in a smooth current path from source to drain of theMOSFET. As illustrated in FIG. 10C, as more gate bias is applied, thebulk channel eventually extends to the accumulation layer.

[0085] As briefly mentioned above, to achieve more efficient shortingchannels, a gate metal with a high work function (such as p⁺polysilicon) and a thinner gate dielectric can be used. The high workfunction gate metal and thinner gate dielectric can deplete more chargeunder the MOS gate at zero gate bias, which turns into a bulk channelwith more free carriers at a positive gate bias (see FIG. 10A). However,providing shorting channels alone may be insufficient to achieve veryhigh effective channel mobilities because the number of free electronsin the bulk channel is very limited. However, shorting channels incombination with a reduction in surface state density, preferably toless than about 10¹² ev⁻¹cm⁻² for within about 0.4 eV of the conductionband energy for 4H polytype silicon carbide, to reduce surfacescattering of the carriers may provide very high effective channelmobilities.

[0086] The on-state I-V characteristics of a device according toembodiments of the present invention are shown in FIG. 13. The devicewas a 3.3 mm by 3.3 mm 4HSiC power MOSFET. As seen in FIG. 13, 10 A ofcurrent is obtained for a 4.4 V forward drop. This device is normally-onat V_(G)=0 V due to the relatively high dose of Nitrogen implanted inthe p-well. However, the device can be made normally-off by reducingthis dose. The electron mobility vs. gate voltage for a 100 μm by 100 μmMOSFET according to embodiments of the present invention is shown inFIG. 14. In the low field regime, extremely high mobility (approachingbulk value) is obtained due to the buried nature of the channel. Athigher gate bias, the mobility reduces due to the channel being confinedto the surface. Even so, a high field mobility of ˜50 cm²/Vs isachieved.

[0087] While embodiments of the present invention have been describedwith reference to particular sequences of operations, as will beappreciated by those of skill in the art, certain operations within thesequence may be reordered while still benefiting from the teachings ofthe present invention. For example, in particular embodiments of thepresent invention, the formation of the n⁺ regions 24 and the p⁺ regions22 may be reversed. Accordingly, the present invention should not beconstrued as limited to the exact sequence of operations describedherein.

[0088] In the drawings and specification, there have been disclosedtypical preferred embodiments of the invention and, although specificterms are employed, they are used in a generic and descriptive senseonly and not for purposes of limitation, the scope of the inventionbeing set forth in the following claims.

That which is claimed is:
 1. A silicon carbide metal-oxide semiconductorfield effect transistor, comprising: a double implant silicon carbideMOSFET, having an n-type silicon carbide drift layer, spaced apartp-type silicon carbide regions in the n-type silicon carbide drift layerand having n-type silicon carbide regions therein, and a nitrided oxidelayer on the n-type silicon carbide drift layer; and n-type shortingchannels extending from respective ones of the n-type silicon carbideregions through the p-type silicon carbide regions and to the n-typesilicon carbide drift layer.
 2. A silicon carbide metal-oxidesemiconductor field effect transistor according to claim 1, wherein thep-type silicon carbide regions comprise spaced apart regions of siliconcarbide having aluminum implanted therein.
 3. A silicon carbidemetal-oxide semiconductor field effect transistor according to claim 1,wherein the n-type shorting channels are extend to but not into then-type silicon carbide drift layer.
 4. A silicon carbide metal-oxidesemiconductor field effect transistor according to claim 1, furthercomprising an epitaxial layer of silicon carbide on the n-type siliconcarbide drift layer between the n-type shorting channels.
 5. A siliconcarbide metal-oxide semiconductor field effect transistor according toclaim 1, further comprising a gate contact on the oxide layer, the gatecontact comprising p-type polysilicon.
 6. A silicon carbide metal-oxidesemiconductor field effect transistor according to claim 1, wherein then-type shorting channels are doped so that the n-type channels are selfdepleted when a zero volt gate bias is applied.
 7. A silicon carbidemetal-oxide field effect transistor according to claim 1, furthercomprising an epitaxial layer of silicon carbide on the n-type siliconcarbide drift layer and the p-type silicon carbide regions and whereinthe n-type shorting channels extend into and/or through the epitaxiallayer of silicon carbide.
 8. A silicon carbide metal-oxide field effecttransistor according to claim 1, wherein the shorting channels have asheet charge of less than about 10¹³ cm⁻².
 9. A silicon carbidemetal-oxide field effect transistor according to claim 1, wherein theshorting channels have a sheet charge corresponding to a silicon carbideepitaxial layer having a thickness of about 3500 Å and a carrierconcentration of about 2×10¹⁶ cm⁻³.
 10. A silicon carbide metal-oxidefield effect transistor according to claim 1, wherein the siliconcarbide comprises 4H polytype silicon carbide and wherein an interfacebetween the oxide layer and the n-type drift layer has an interfacestate density of less than 10¹² eV⁻¹cm⁻² for energy levels between about0.3 and about 0.4 eV of a conduction band energy of 4H polytype siliconcarbide.
 11. A silicon carbide metal-oxide field effect transistoraccording to claim 1, wherein the nitride oxide comprises at least oneof an oxide-nitride-oxide structure and an oxynitride.
 12. A siliconcarbide device comprising: a drift layer of n-type silicon carbide;first regions of p-type silicon carbide in the drift layer, the firstregions of p-type silicon carbide being spaced apart and havingperipheral edges which define a region of the drift layer therebetween;first regions of n-type silicon carbide having a carrier concentrationgreater than a carrier concentration of the drift layer in the firstregions of p-type silicon carbide and spaced apart from the peripheraledges of the first regions of p-type silicon carbide; second regions ofn-type silicon carbide having a carrier concentration less than thecarrier concentration of the first regions of n-type silicon carbide andwhich extend from the first regions of n-type silicon carbide to theperipheral edges of the first regions of p-type silicon carbide; and anitrided oxide layer on the drift layer, the first regions of n-typesilicon carbide and the second regions of n-type silicon carbide.
 13. Asilicon carbide device according to claim 12, wherein the second regionsof n-type silicon carbide have a sheet charge of less than about 10¹³cm⁻².
 14. A silicon carbide device according to claim 13, wherein thesecond regions of n-type silicon carbide have a depth of from about 0.05μm to about 1 μm.
 15. A silicon carbide device according to claim 14,wherein the second regions of n-type silicon carbide extend a distanceof from about 0.5 μm to about 5 μm from the first regions of n-typesilicon carbide to the peripheries of the first regions of p-typesilicon carbide.
 16. A silicon carbide device according to claim 12,wherein the second regions of n-type silicon carbide have a sheet chargecorresponding to a silicon carbide epitaxial layer having a thickness ofabout 3500 Å and a carrier concentration of about 2×10 cm⁻³.
 17. Asilicon carbide device according to claim 12, wherein an interface statedensity of an interface between the oxide layer and the drift layer, thefirst regions of n-type silicon carbide and the second regions of n-typesilicon carbide is less than about 10¹² eV⁻¹cm⁻² between about 0.3 andabout 0.4 eV of the conduction band energy of 4H polytype siliconcarbide.
 18. A silicon carbide device according to claim 12, furthercomprising second regions of p-type silicon carbide disposed inrespective ones of the first regions of p-type silicon carbide, whereinthe second regions of p-type silicon carbide have a carrierconcentration greater than the carrier concentration of the firstregions of silicon carbide, the second regions of silicon carbide beingadjacent the first regions of n-type silicon carbide and opposite thesecond regions of n-type silicon carbide.
 19. A silicon carbide deviceaccording to claim 12, further comprising a gate contact on the oxidelayer.
 20. A silicon carbide device according to claim 19, wherein thegate contact is p-type polysilicon.
 21. A silicon carbide deviceaccording to claim 12, wherein the first regions of p-type siliconcarbide are spaced apart by a distance of from about 1 μm to about 10μm.
 22. A silicon carbide device according to claim 21, wherein thefirst regions of p-type silicon carbide have a carrier concentration offrom about 1×10¹⁶ to about 2×10^(·)cm⁻³.
 23. A silicon carbide deviceaccording to claim 12, further comprising contacts on the first regionof p-type silicon carbide and the first region of n-type siliconcarbide.
 24. A silicon carbide device according to claim 12, furthercomprising: a layer of n-type silicon carbide having a carrierconcentration greater than the carrier concentration of the drift layerand disposed adjacent the drift layer opposite the oxide layer; and adrain contact on the layer of n-type silicon carbide.
 25. A siliconcarbide device according to claim 12, further comprising an epitaxiallayer of silicon carbide on the first p-type regions and the drift layerof n-type silicon carbide, wherein the second regions of n-type siliconcarbide extend into the epitaxial layer, the first regions of n-typesilicon carbide extend through the epitaxial layer and the oxide layeris on the epitaxial layer, the first regions of n-type silicon carbideand the second regions of n-type silicon carbide.
 26. A silicon carbidedevice according to claim 25, where in the epitaxial layer comp risesundoped silicon carbide.
 27. A silicon carbide device according to claim25, wherein the epitaxial layer of silicon carbide comprises anepitaxial layer of silicon carbide having a thickness of from about 0.05μm to about 1 μm.
 28. A silicon carbide device according to claim 27,wherein the epitaxial layer of silicon carbide comprises an epitaxiallayer of silicon carbide having a thickness of from about 1000 to about5000 Å.
 29. A silicon carbide device according to claim 25, wherein theepitaxial layer comprises n-type silicon carbide having a sheet chargeof less than about 10¹³ cm⁻².
 30. A silicon carbide device according toclaim 25, wherein the second regions of n-type silicon carbide have asheet charge of less than about 10¹³ cm⁻².
 31. A silicon carbide deviceaccording to claim 30, wherein the second regions of n-type siliconcarbide have a depth of from about 0.05 μm to about 1 μm.
 32. A siliconcarbide device according to claim 31, wherein the second regions ofn-type silicon carbide extend a distance of from about 0.5 μm to about 5μm from the first regions of n-type silicon carbide to the peripheriesof the first regions of p-type silicon carbide.
 33. A silicon carbidedevice according to claim 25, wherein an interface state density of aninterface between the oxide layer and the epitaxial layer, the firstregions of n-type silicon carbide and the second regions of n-typesilicon carbide is less than about 10¹² eV⁻¹cm⁻² between about 0.3 andabout 0.4 eV of the conduction band energy of 4H polytype siliconcarbide.
 34. A silicon carbide device according to claim 25, furthercomprising second regions of p-type silicon carbide disposed inrespective ones of the first regions of p-type silicon carbide, whereinthe second regions of p-type silicon carbide have a carrierconcentration greater than the carrier concentration of the firstregions of silicon carbide, the second regions of silicon carbide beingadjacent the first regions of n-type silicon carbide and opposite thesecond regions of n-type silicon carbide.
 35. A silicon carbide deviceaccording to claim 34, further comprising: windows in the epitaxiallayer positioned to expose the second regions of p-type silicon carbide;and first source contacts within the window on the second regions ofp-type silicon carbide and on the first regions of n-type siliconcarbide.
 36. A silicon carbide device according to claim 25, furthercomprising a gate contact on the oxide layer.
 37. A silicon carbidedevice according to claim 36, wherein the gate contact is p-typepolysilicon.
 38. A silicon carbide device according to claim 25, whereinthe first regions of p-type silicon carbide are spaced apart by adistance of from about 1 μm to about 10 μm.
 39. A silicon carbide deviceaccording to claim 38, wherein the first regions of p-type siliconcarbide have a carrier concentration of from about 1×10¹⁶ to about2×10¹⁹ cm⁻³.
 40. A silicon carbide device according to claim 25, furthercomprising: a layer of n-type silicon carbide having a carrierconcentration greater than the carrier concentration of the drift layerand disposed adjacent the drift layer opposite the oxide layer; and adrain contact on the layer of n-type silicon carbide.
 41. A siliconcarbide metal-oxide field effect transistor according to claim 12,wherein the nitride oxide layer comprises at least one of anoxide-nitride-oxide structure and an oxynitride layer.
 42. A method offabricating a silicon carbide device, the method comprising: implantingp-type impurities in a layer of n-type silicon carbide so as to providefirst regions of p-type silicon carbide, the first regions of p-typesilicon carbide being spaced apart and having peripheral edges whichdefine a region of the layer of n-type silicon carbide therebetween;implanting n-type impurities into the first regions of p-type siliconcarbide to provide first regions of n-type silicon carbide having acarrier concentration greater than a carrier concentration of the layerof silicon carbide, the first regions of n-type silicon carbide beingspaced apart from the peripheral edges of the first regions of p-typesilicon carbide; implanting n-type impurities into the first regions ofp-type silicon carbide to provide second regions of n-type siliconcarbide having a carrier concentration less than the carrierconcentration of the first regions of n-type silicon carbide and whichextend from the first regions of n-type silicon carbide to theperipheral edges of the first regions of p-type silicon carbide; andpatterning an oxide layer on the drift layer, the first regions ofn-type silicon carbide and the second regions of n-type silicon carbideso as to provide a gate oxide.
 43. A method according to claim 42,wherein the steps of implanting p-type impurities, implanting n-typeimpurities to provide first regions of n-type silicon carbide andimplanting n-type impurities to provide second regions of n-type siliconcarbide, comprise: patterning a first mask on the layer of n-typesilicon carbide, the first mask having openings corresponding to thefirst regions of p-type silicon carbide so as to expose portions of thelayer of n-type silicon carbide; then implanting p-type impurities intothe layer of n-type silicon carbide utilizing the first mask; thenimplanting n-type impurities into the first regions of p-type siliconcarbide utilizing the first mask; then patterning a second mask on thelayer of n-type silicon carbide, the second mask having openingscorresponding to the first regions of n-type silicon carbide so as toexpose portions of the layer of n-type silicon carbide having the p-typeand n-type impurities implanted therein; then implanting n-typeimpurities into the layer of n-type silicon carbide utilizing the secondmask.
 44. The method of claim 43, wherein the step of implanting n-typeimpurities into the layer of n-type silicon carbide utilizing the firstmask is followed by the step of activating the implanted impurities byannealing at a temperature of at least about 1500° C.
 45. The method ofclaim 44, wherein the p-type impurities comprise aluminum.
 46. Themethod of claim 43, wherein the second mask is patterned so that thesecond regions of n-type silicon carbide extend a distance of from about0.5 μm to about 5 μm from the first regions of n-type silicon carbide tothe peripheries of the first regions of p-type silicon carbide.
 47. Themethod of claim 42, wherein the step of implanting n-type impurities toprovide second regions of n-type silicon carbide, comprises implantingimpurities so that the second regions of n-type silicon carbide have asheet charge of less than about 13 cm⁻².
 48. The method of claim 47,wherein the step of implanting n-type impurities to provide secondregions of n-type silicon carbide, further comprises implanting n-typeimpurities utilizing an implant energy so as to provide second regionsof n-type silicon carbide have a depth of from about 0.05 μm to about 1μm.
 49. The method of claim 42, wherein the step of patterning an oxidelayer comprises the step of thermally growing an oxide layer.
 50. Themethod of claim 49 wherein the step of thermally growing an oxide layercomprises the step of thermally growing an oxide layer in an NO or anN₂O environment.
 51. The method of claim 49, wherein the step ofthermally growing an oxide layer comprises the step of thermally growingan oxynitride layer.
 52. The method of claim 42, wherein the step ofpatterning an oxide layer comprises the step of forming anoxide-nitride-oxide (ONO) layer.
 53. The method of claim 42, furthercomprising the step of annealing the oxide layer in at least one of anNO environment or an N₂O environment.
 54. The method of claim 53,wherein the step of annealing provides an interface state density of aninterface between the oxide layer and the drift layer, the first regionsof n-type silicon carbide and the second regions of n-type siliconcarbide of less than about 10¹² eV⁻¹cm⁻² within about 0.4 eV of theconduction band energy of 4H polytype silicon carbide.
 55. The method ofclaim 42, further comprising implanting p-type impurities into the layerof n-type silicon carbide so as to provide second regions of p-typesilicon carbide disposed in respective ones of the first regions ofp-type silicon carbide, wherein the second regions of p-type siliconcarbide have a carrier concentration greater than the carrierconcentration of the first regions of silicon carbide, the secondregions of silicon carbide being adjacent the first regions of n-typesilicon carbide and opposite the second regions of n-type siliconcarbide.
 56. The method of claim 42, further comprising forming a gatecontact on the gate oxide layer.
 57. The method of claim 56, whereinstep of forming a gate contact comprises the step of patterning p-typepolysilicon so as to provide a gate contact on the gate oxide layer. 58.The method of claim 43, wherein the first mask has openings which arespaced apart by a distance of from about 1 μm to about 10 μm.
 59. Themethod of claim 42, further comprising: implanting n-type impuritiesinto a face of the layer of n-type silicon carbide opposite the oxidelayer so as to provide a second layer of n-type silicon carbide having acarrier concentration greater than the carrier concentration of thelayer of n-type silicon carbide; and forming a drain contact on thesecond layer of n-type silicon carbide.
 60. The method of claim 42,wherein the layer of n-type silicon carbide comprises a silicon carbidesubstrate.
 61. The method of claim 42, wherein the steps of implantingp-type impurities, implanting n-type impurities to provide first regionsof n-type silicon carbide and implanting n-type impurities to providesecond regions of n-type silicon carbide, comprise: patterning a firstmask on the layer of n-type silicon carbide, the first mask havingopenings corresponding to the first regions of p-type silicon carbide soas to expose portions of the layer of n-type silicon carbide; thenimplanting p-type impurities into the layer of n-type silicon carbideutilizing the first mask; then annealing the layer of n-type siliconcarbide and the first regions of p-type silicon carbide at a temperatureof at least about 1500° C.; then growing an epitaxial layer of siliconcarbide on the layer of n-type silicon carbide and the first regions ofp-type silicon carbide; then patterning a second mask on the layer ofn-type silicon carbide, the second mask having openings corresponding tothe second regions of n-type silicon carbide so as to expose portions ofthe first regions of p-type silicon carbide; implanting n-typeimpurities into the epitaxial layer n-type silicon carbide utilizing thesecond mask; then patterning a third mask on the layer of n-type siliconcarbide, the third mask having openings corresponding to the firstregions of n-type silicon carbide so as to expose portions of the firstregions of p-type silicon carbide; implanting n-type impurities into thefirst regions of p-type silicon carbide and the epitaxial layer ofsilicon carbide utilizing the third mask; and wherein the step ofpatterning an oxide layer comprises patterning an oxide layer on theepitaxial layer, the first regions of n-type silicon carbide and thesecond regions of n-type silicon carbide to provide a gate oxide. 62.The method of claim 61, wherein the step of growing an epitaxial layerof silicon carbide comprises growing an undoped epitaxial layer ofsilicon carbide.
 63. The method of claim 61, wherein the step of growingan epitaxial layer of silicon carbide comprises growing an epitaxiallayer of silicon carbide having a sheet charge of less than about 10¹³cm⁻².
 64. The method of claim 61, wherein the step of growing anepitaxial layer of silicon carbide comprises growing an epitaxial layerof silicon carbide having a thickness of from about 0.05 μm to about 1μm.
 65. The method of claim 64, wherein the step of growing an epitaxiallayer of silicon carbide comprises growing an epitaxial layer of siliconcarbide having a thickness of from about 1000 to about 5000 Å.
 66. Themethod of claim 61, wherein the p-type impurities comprise aluminum. 66.The method of claim 61, wherein the third mask is patterned so that thesecond regions of n-type silicon carbide extend a distance of from about0.5 μm to about 5 μm from the first regions of n-type silicon carbide tothe peripheries of the first regions of p-type silicon carbide.
 68. Themethod of claim 61, wherein the step of implanting n-type impurities toprovide second regions of n-type silicon carbide, comprises implantingimpurities so that the second regions of n-type silicon carbide have asheet charge of less than about 10¹³ cm⁻².
 69. The method of claim 68,wherein the step of implanting n-type impurities to provide secondregions of n-type silicon carbide, further comprises implanting n-typeimpurities utilizing an implant energy so as to provide second regionsof n-type silicon carbide have a depth of from about 0.05 μm to about 1μm.
 70. The method of claim 61, wherein the step of patterning an oxidelayer comprises the step of thermally growing an oxide layer.
 71. Themethod of claim 70, wherein the step of thermally growing an oxide layercomprises thermally growing an oxide layer in an NO or an N₂Oenvironment.
 72. The method of claim 70, wherein the step of thermallygrowing an oxide layer comprises the step of thermally growing anoxynitride layer.
 73. The method of claim 61, wherein the step ofpatterning an oxide layer comprises the step of forming anoxide-nitride-oxide (ONO) layer.
 74. The method of claim 61, furthercomprising the step of annealing the oxide layer in at least one of anNO environment or an N₂O environment.
 75. The method of claim 74,wherein the step of annealing provides an interface state density of aninterface between the oxide layer and the drift layer, the first regionsof n-type silicon carbide and the second regions of n-type siliconcarbide of less than about 10¹² eV⁻¹cm⁻² within from about 0.3 to about0.4 eV of the conduction band energy of 4H polytype silicon carbide. 76.The method of claim 61, wherein the step of annealing is preceded by thesteps of: patterning a fourth mask, the fourth mask being on the layerof n-type silicon carbide and the first regions of p-type siliconcarbide and having opening therein corresponding to second regions ofp-type silicon carbide disposed in respective ones of the first regionsof p-type silicon carbide the second regions of silicon carbide beingadjacent the first regions of n-type silicon carbide and opposite thesecond regions of n-type silicon carbide; and implanting p-typeimpurities utilizing the fourth mask so that the second regions ofp-type silicon carbide have a carrier concentration greater than thecarrier concentration of the first regions of silicon carbide.
 77. Themethod of claim 76, further comprising: forming windows in the epitaxiallayer positioned to expose the second regions of p-type silicon carbide;and forming contacts within the window on the second regions of p-typesilicon carbide and the first regions of n-type silicon carbide.
 78. Themethod of claim 61, further comprising forming a gate contact on thegate oxide layer.
 79. The method of claim 78, wherein step of forming agate contact comprises the step of patterning p-type polysilicon so asto provide a gate contact on the gate oxide layer.
 80. The method ofclaim 61, wherein the first mask has openings which are spaced apart bya distance of from about 1 μm to about 10 μm.
 81. The method of claim61, further comprising: implanting n-type impurities into a face of thelayer of n-type silicon carbide opposite the oxide layer so as toprovide a second layer of n-type silicon carbide having a carrierconcentration greater than the carrier concentration of the layer ofn-type silicon carbide; and forming a drain contact on the second layerof n-type silicon carbide.
 82. The method of claim 61, wherein the layerof n-type silicon carbide comprises a silicon carbide substrate.
 83. Asilicon carbide metal-oxide semiconductor field effect transistor,comprising: a silicon carbide MOSFET, having an n-type silicon carbidedrift layer, spaced apart p-type silicon carbide regions in the n-typesilicon carbide drift layer and having n-type silicon carbide regionstherein, and a nitrided oxide layer on the n-type silicon carbide driftlayer; and a region between the n-type silicon carbide regions and thedrift layer and is adjacent the nitrided oxide layer that is configuredto self deplet upon application of a zero gate bias.
 84. A siliconcarbide metal-oxide semiconductor field effect transistor according toclaim 83, wherein the p-type silicon carbide regions comprise spacedapart regions of silicon carbide having aluminum implanted therein. 85.A silicon carbide metal-oxide semiconductor field effect transistoraccording to claim 83, wherein the region that is configured toself-deplete extends to but not into the n-type silicon carbide driftlayer.
 86. A silicon carbide metal-oxide semiconductor field effecttransistor according to claim 83, further comprising an epitaxial layerof silicon carbide on the n-type silicon carbide drift layer between thep-type regions.
 87. A silicon carbide metal-oxide semiconductor fieldeffect transistor according to claim 83, wherein the region that isconfigured to self-deplete comprises a region of silicon carbide havinga sheet charge corresponding to a sheet charge of an epitaxial layer ofsilicon carbide having a thickness of about 3500 Å and carrierconcentration of about 2×10¹⁶ cm⁻³.
 88. A silicon carbide metal-oxidesemiconductor field effect transistor according to claim 83, furthercomprising a gate contact on the oxide layer, the gate contactcomprising p-type polysilicon.
 89. A silicon carbide metal-oxide fieldeffect transistor according to claim 83, wherein the silicon carbidecomprises 4H polytype silicon carbide and wherein an interface betweenthe oxide layer and the n-type drift layer has an interface statedensity of less than 10¹² eV⁻¹cm⁻² for energy levels between about 0.3and about 0.4 eV of a conduction band energy of 4H polytype siliconcarbide.